RISC Simulator with Fetch/Execute and register based CPU model

The LMC is currently used by schools to show assembly language and "how a computer works". Unfortunately as a computer model it is very out of date and is not binary based. (The last single accumulator machine I used was designed around 1965.)

At least one exam board is moving to include some ARM like instructions and so I have converted my LMC Simulator to have a more modern multi-register instruction set with a stack, subroutines, logical instructions and both immediate and indirect addressing.

You can find the simulator at www.peterhigginson.co.uk/RISC/.

You can find a description of the instruction set at www.peterhigginson.co.uk/RISC/instruction_set.pdf and some notes on the design at www.peterhigginson.co.uk/RISC/RISC_simulator_design.pdf and both of these links can also be obtained by clicking on the HELP button.

Even though I have tested it until I'm going round in circles (e.g. I fix an alignment on the iPAD and it throws out the Chrome display), I am sure there still will be bugs. Please let me know of any you find.

I don't have many code examples yet and I'm wary that with the LMC teachers wanted to set simple examples to students rather than have them all given. So the one complex program I have included is one of my instruction tests (and I'm still impressed by the multi-register push at instruction 6).

In V1.02 I have changed the assembler to highlight the line in error (it stops at the first) and not leave a part assembled program in memory. Also if you attempt to use a register name as a label you will get an error

June 2022 - I have just released V1.06. See the help pages for a list of changes.